Reference no: EM13336163

1- The transistor characteristics i_D versus V_ds for an NMOS device are shown in the figure below.

(a)  Is this an enhancement-mode or depletion-mode device?

(b) Determine the values for K_n and V_TN

(c)  Determine i_D(sat) for v_Gs = 3.5 V and v_Gs = 4.5 V.

2- The threshold voltage of each transistor in the figure below is V_Tn = 0.4V. Determine the region of operation of the transistor in each circuit.

3- The threshold voltage of each transistor in the figure below is V_Tp = -0.4V. Determine the region of operation of the transistor in each circuit.

4- The parameters of an n-channel enhancement-mode MOSFER are V_TN = 0.5V, k'_n = 120μA/v², and W/L = 4. What is the maximum value of λ and the minimum value of V_A such that for V_Gs = 2V, r_o ≥ 200kΩ?

5- An enhancement-mode NMOS transistor has parameters V_TNO = 0.8 V, γ = 0.8 V^1/2, and Φ_f. = 0.35 V. At what value of V_SB will the threshold voltage change by 2 V due to the body effect?

6- For the circuit in the figure below, sketch i_d versus v_s for v_s varying from 0 to V_DD. Clearly label your sketch.

7- For the circuit in the figure below, find an expression for v_DS in terms of i_D. Sketch and clearly label a graph for v_DS versus i_D.

8- The PMOS transistor in the figure below has V_TP = -0.5V. As the gate voltage v_G is varied from +2.5 V to 0 V, the transistor moves through all of its three possible modes of operation. Specify the value of v_G at which the device changes modes of operation.

9- All the transistors in the circuits shown in the figure below have the same values of |V_T|, k', W/L, and A. Moreover, A is negligibly small. All operate in saturation at I_D = 1 and |VGS| = |V_DS| = 3 V.

(a)  Find the voltages V₁, V₂, V₃, and V₄.

(b)  If |V_T| = 1 V and 1 = 2 mA, how large a resistor can be inserted in series with each drain connection while maintaining saturation?

(c)  If the current source 1 requires at least 2 V between its terminal to operate properly, what is the largest resistor that can be placed in series with each MOSFET source while ensuring saturated-mode operation of each transistor at I_D = 1? In this limiting situation, what do V_I, V₂, V₃, and V₄ become?

10- For the transistor in the circuit below, the parameters are V_TN = 0.4 V k'_n = 120 μA/V² and W/L = 25. Determine V_GS, I_D, and V_Ds. Sketch the load line and plot the Q- point.

11- Design the circuit in the figure below so that V_SD = 2.5 V. The current in the bias resistors should be no more than 10 percent of the drain current. The transistor parameters are V_TP = 1.5 V and K_p, = 0.5 mA/v²

12- Consider the circuit in the figure below.

(a) Design the circuit such that I_DQ = 0.25 mA and V_D = -2 V. The nominal transistor parameters are V_TP = -1.2 V, K'_p, = 35 μA/V² and ^vi_L = 15. Sketch the load line and plot the Q-point.

(b) Determine the maximum and minimum Q-point values if the tolerance of the k'_p, parameter is ±5 percent.

13-Consider the circuit in the figure below. The transistor parameters are V_TP = -0.8 V, and K_P = 200 μA/V² Determine V_s and V_SD.

14- The transistor in the circuit in the figure below is used to turn the LED on and off. The transistor parameters are V_TN = 0.6 V, k_n' = 80, and A = 0. The diode cut-in voltage is Vy = 1.6 V. Design RD and the transistor width-to-length ratio such that I_D = 12 mA for V₁ = 5 V and V_DS = 0.15 V.

15- For the circuit shown in the figure below, find the labeled node voltages. The NMOS transistors have V_TN = 1 V and k'n W/L = 2 mA/V². Assume λ = 0.