Reference no: EM132463316

ELEC S241F Electronic Circuit Design Assignment - The Open University of Hong Kong, Hong Kong

There are THREE sections in this assignment. You should answer all NINE (9) questions in this assignment.

SECTION A -

Question 1 - Consider the circuit in Figure Q1. Given R₁ = 2 k?, R₂ = 2 k?, R₃ = 4 k?, R₄ = 1 k?. The diodes D₁ and D₂ are assumed to have V_γ = 0.7 V.

(a) Assume that D₁ is ON and D₂ is OFF, determine the voltages V_A, V_B and current I_D1.

(b) Use OrCAD to build the circuit in Figure Q1 to verify your answers in (a), i.e. find V_A, V_B and I_D1.

Question 2 - Figure Q2 shows a NMOS common-source amplifier circuit. The NMOS transistor parameters are: V_TN = +1.0 V, K_n = 0.5 mA/V² and λ = 0. Given: V_DD = +8 V, V_GG = +2 V, R_G = 3 k? and your R_D.

Remark: You must use your own R_D to finish this assignment.

(a) Assume that the NMOS is biased in the saturation region. Find the Q-point parameters: I_DQ, V_GSQ, V_DSQ.

(b) Show your assumption is correct.

Question 3 - A 6-bit digital-ramp A-D converter has a range of [0, +12V].

(a) What is the step size ? of this converter?

(b) State in binary form the final digital value that this A-D produces for an input voltage of +8.4V. Show all your calculations.

(c) Given the clock period is 1 µs, what is the maximum conversion time taken for this A-D converter?

Question 4 - A circuit is constructed from three flip-flops, as shown in Figure Q4, and outputs are taken from the Q output of each flip-flop. The initial values of these outputs are Q_A = 0, Q_B = 1, Q_C = 1 as shown. The flip-flops are all clocked from a common clock signal.

What will be the outputs after the receipt of four clock pulses?

Question 5 - Consider the circuit in Figure Q5. Assume that the op amp is ideal.

(a) Using the phasor to prove that the voltage gain transfer function H(f) = V_out/V_in is given by

H(f) = - (R₂/R₁)/(1+j2πf(L/R₁))

(b) How does H(f) change with frequency f increasing from 0 to infinity?

SECTION B -

Question 6 - A sequential machine will be designed to control the sequence of a lighting system. There will be two inputs A and B, and three outputs R, S and T. A state-transition diagram of this machine is shown in Figure Q6(a).

(a) In your answer book complete a copy of the state-table shown in Figure Q6(b) (attached).

(b) The partially completed state-assignment table for this system is shown in Figure Q6(c) (attached). The combination CD represents the present state and EF represents the next state, i.e. "state a" is assigned 00, "state b" 01 etc. In your answer construct a table which shows the input columns ABCD and has just the completed output columns for E, F and S.

(c) Use the Karnaugh map to find simplified Boolean expressions for R.

(d) Use two positive edge-triggered JK-type flip-flops (inputs J₁ K₁, J₂, K₂) to implement this sequential machine. Write down the Boolean expression for J₁ K₁, J₂ and K₂ in terms of A, B, C and D.

Question 7 -

(a) Consider the BJT circuit in Figure Q7. Let R1 = 7 k?, R2 = 3 k?, Vcc = +10 V. Assume that V_BE(on) = 0.7 V, β = 100, and VA = ∞. You can assume that the impedances of capacitors C1, C2 and C3 are negligible in the operating frequency.

Given the Q-point parameters are I_CQ = 2.50 mA and V_CEQ = 6.0 V.

(i) What is the operating mode of the BJT? Explain your answer.

(ii) Find the values of resistors R_C and R_E.

(b) Draw the small-signal equivalent circuit of Figure Q7.

(c) Find the small-signal voltage gain of the circuit.

(d) Use OrCAD to build the circuit as shown in Figure Q7. You can take v_in = 1 mV, C1 = C2 = C3 = 100 µF, R1 = 7 k?, R2 = 3 k?, R_L = 10 k? and your R_C and R_E in part (a)(ii).

Hint: You should use QbreakN in the breakout library to model your NPN transistor.

(i) Find the operating conditions of the circuit (i.e. the d.c. voltages at each node of the circuit). Print out both your schematics and output file.

(ii) Find the gain of the amplifier, i.e. V_out/V_in. Print out a plot of gain vs frequency over frequency 100 Hz to 1 MHz.

You must submit the schematic, output file and frequency plot of your simulation results in pdf format.

SECTION C -

Question 8 - This question investigates the frequency response of a non-ideal op amp (uA741 in OrCAD) as shown in Figure Q8(a). You are going to find the open-loop low-frequency gain A_O and open-loop (3dB) bandwidth f_O of this non-ideal op amp using OrCAD.

Hint: You should use uA741 in the eval library to model your op amp.

The uA741 op amp has an open-loop voltage transfer function given by A_V = A_o/(1+j(f/f_O)).

Instructions:

1. Use OrCAD to build a circuit as shown in Figure Q8(b) (attached). Given V_in = 10 µV and R₁ = 10 k?.

2. Create a new simulation profile. In the resulting Simulation Settings window, select AC Sweep/Noise as the analysis type and leave the options as General Settings. Set the Start Frequency to 1 and the End Frequency to 100meg.

3. Set the Point/Decade to 100. Leave the AC Sweep Type settings at Logarithmic and Decade. Save your setting and run the simulation.

You must submit both the schematic and output file of your simulation results in pdf format.

(a) Obtain a plot of the magnitude of gain |V_out/V_in| in dB vs frequency.

(b) Use cursor to find the open-loop low-frequency gain (in dB) from your plot. Find A_O (not in dB).

(c) Use cursor to find the open-loop (3-dB) bandwidth f_O.

(d) Find the gain-bandwidth of this op amp.

(e) (i) Use your own A_O and f_O to express A_V.

(ii) Sketch the Bode plot of the magnitude of AV with frequency. On the sketch indicate the maximum magnitude of gain, any corner frequencies, and the values of any slopes. Use decibels for the gain scale and a logarithmic frequency scale covering the range 1 Hz to 10 MHz

Question 9 - The non-ideal op amp (uA741 in OrCAD) in Question 8 is used in a series-shunt feedback configuration (non-inverting amplifier) in Figure Q9. Given V_in = 1 mV, R₂ = 20 k? and your own R₁, where

(a) Use OrCAD to build the circuit in Figure Q9. You can refer to your simulation setting in Question 8. You should simulate the frequency response over the range 1 Hz to 100 MHz, with 100 points per decade for each gain setting.

(i) Obtain a plot of the magnitude of amplifier gain |V_out/V=| in dB.

(ii) Find the magnitude of the closed-loop gain A_CL.

(iii) Find 3 dB bandwidth f_CL for this non-inverting amplifier.

You must submit both the schematic and output file of your simulation results in pdf format.

(b) Compute the voltage gain of this non-inverting amplifier in Figure Q9. Compare it with your simulated results in (a)(ii).

Attachment:- Electronic Circuit Design Assignment File.rar