Draw the schematic circuit

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Reference no: EM13688571

Build a Finite State Machine and simulate it to prove that it performs its intended function.

The following state diagram is to be simulated.

1586_Build a Finite State Machine.png

Develop a hand drawn timing diagram for the FSM in terms of the clock, the inputs, output, and secondary state variables that will test the FSM.

1. Develop the Boolean equations for a T type Flip Flop realisation.

2. Draw the schematic circuit

3. Build up a Verilog HDL file to simulate the system. Your simulation will contain the Verilog module of the FSM and a test bench to test out your design. The test bench should contain a suitable test strategy to test all aspects of the design.

4. Comment on the results you obtain in terms of the timing waveforms (from the simulator) and those you produced in 1.

Reference no: EM13688571

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