Draw the common emitter transistor bias configuration

Reference no: EM131290526

ASSINGMENT

1. Draws the Common Emitter transistor bias configuration as shown in figure 1 using PSpice. Given V_cc =12V. R_c = 4k?. By using different, R_B, simulates and records the importance values as shown in Table 1. Plot the DC load line using at least 5 Q-points. Ignore the base current curve. Use any suitable NPN transistor.

Figure 1

Figure 2

Table

R_B	I_B	I_C	V_CE
10M?
1M?

2. Base on the schematic in the Question 1. Modify the circuit to a signal amplifier circuit as shown in Figure 3. Select three Q-point in load line as shown in Figure 2. For every point of Q-point selected, simulate the signal amplifier. For example, select Q point at V_CE=0.5*V_CC. Put any value of input signal, V2.(try 1mV). Run the simulation. Observe the output voltage at R3. Increase the input signal, V2 until the output at R3 is distorted. Record the maximum input signal and output voltage at R3. Print the waveform's input and output. Repeat the same proses for others two Q point. Conclude where the best Q point is for maximum output and explains why.

Figure 3

Reference no: EM131290526

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