Draw logic gate implementation for half adder

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Reference no: EM132840572

Assignments for Very Large Scale Integration

G1 Adder (half adder & full adder)
A) Write the truth table for both half adder & full adder
B) Draw logic gate implementation for half adder & full adder
C) Verilog code for half adder & full adder
D) VHDL code for half adder & full adder

G2 Substractor (half &full)
A) Write the truth table for both half substractor & full substractor
B) Draw logic gate implementation for half substractor & full substractor
C) Verilog code for half substractor & full substractor
D) VHDL code for half substractor& full substractor

G3Encoder(8:3) & Decoder (3:8)
A) Write the truth table for both Encoder(8:3) & Decoder(3:8)
B) Draw logic gate implementation for Encoder(8:3) & Decoder(3:8)
C) Verilog code for Encoder(8:3) & Decoder(3:8)
D) VHDL code for Encoder(8:3) & Decoder(3:8)

G4Multiplexer (16:1) &De-multiplexer (1:16)
A) Write the truth table for both Multiplexer (16:1) &De-multiplexer (1:16)
B) Draw logic gate implementation for Multiplexer (16:1) &De-multiplexer (1:16)
C) Verilog code for Multiplexer (16:1) &De-multiplexer (1:16)
D) VHDL code for Multiplexer (16:1) &De-multiplexer (1:16)

G5 8bit D Flipflop, T Flipflop and JK Flipflop
A) Write the truth table for both 8bit D Flip flop, T Flip flop and JK Flip flop
B) Draw logic gate implementation for 8bit D Flip flop, T Flip flop and JK Flip flop
C) Verilog code for 8bit D Flip flop, T Flip flop and JK Flip flop
D) VHDL code for 8bit D Flip flop, T Flip flop and JK Flip flop

Reference no: EM132840572

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