Reference no: EM131005332
1. Analyze the feedback sequential circuit shown in Figure 1.
a. Break the feedback loops (Y1, Y2, Y3) and write the next state equations.
b. Construct the transition/output table, showing each of the total stable states. Assume Y3 is high-order (most significant) bit.
c. This circuit has multiple flaws as a fundamental mode circuit. Explain what is wrong with this circuit based upon your results from (b). Be specific.
d. What needs to change to fix this circuit? Give one or more specific examples.
2. Design a fundamental mode circuit that will continuously cycle with a 3 bit output shown below while the input X=1. The circuit will stop at it's present count when X=0. Thus, the stable states occur only when X=0. The count sequence allows only one bit to change per cycle. The count sequence is 000, 001, 011, 010, 110, 111, 101, 100, 000, etc.
a. Develop the flow table. Assume the state variables Y3, Y2, Y1, with Y3 being the high order bit. Identify the stable states.
b. Determine the reduced switching expressions for the next state equations using K-Maps.
c. Draw the circuit diagram (neatly). Indicate the breakpoints in the feedback loops that correspond to the encoded state table.
3. A flow table is given in Figure 2 below. Find an assignment of state variables that avoids all critical races. You may add additional states as necessary (using a few state variables as possible).
a. Assign the all-0s combination to state A. Draw an adjacency diagram for the original flow table.
b. Write the modified flow table and another adjacency diagram to support your final state assignment.
4. Create a Verilog simulation model of a 3 bit sequential counter. The current state values (e.g., the flip flop outputs) should reflect the count output. The count sequence for the code is 000, 001, 011, 010, 110, 100, 101, 111. Include a $Monitor print statement that includes your name, ECE class section number and date with approximate time of run. You can modify the Lecture 17 example models for your implementation. Additional design requirements are as follows:
a. Implement a clock with a 10ns clock period with balanced 5ns high and low . The simulation should be positive edge triggered.
b. Follow the example model(s) by including an initial 15ns initialization period.
c. Implement a control input, C, that will stop the count sequence when C=0. The sequence will continue when C=1. Using the C input only, your simulation count should pause for 30 ns after 011 and 100.
d. Create a $Monitor statement to print the value of C, current time and the current count for each 10 ns clock cycle. The simulation should stop when the final count is reached. Show a printout of your console listing AND the wave diagram (showing clock, C, and count signals).
5. Create a Verilog model for the sequence detector state and output table shown in Figure 3. Your test bench should include a verify task that validates the output for the given input at each clock cycle. You can modify the Lecture 17 example models for your implementation. Include a $Monitor statement that prints your name, section number, date and approximate time of model run.
(a). Use the test sequence shown below. This sequence will result in a valid test for each transition in your state table. Show a printout of your console listing that captures the current input, output and expected output for each clock cycle.
(b). Once you have completed a valid run with the test sequence, modify your model to replace next state 001 on row 010 under X=1 with 100. This should cause your test bench to fail and stop the simulation when the error is encountered. Repeat for the same test sequence. Show a printout of your console listing (it should stop due to the break in the state machine).
