Draw a schematic for this basic shifter cell

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Reference no: EM131385942

(Shift-register Design) Design the basic cell of a universal shift register to the following specifications. The internal storage elements will be positive edge-triggered D flip-flops. Besides the clock, the shifter stage has two external control inputs, S0 and S1, and three external data inputs, SR, SL, and DI. SR is input data being shifted into the cell from the right, SL is data being shifted from the left, and DI is parallel-load data. The current value of the flip-flop will be replaced according to the following settings of the control signals: S₀ = S₁ = 0: replace D with D_I; S₀ = 0, S₁ = 1: replace D with S_L; S₀ = 1, S₁ = 0: replace D with SR; S₀ = S₁ = 1: hold the current state. Draw a schematic for this basic shifter cell.

Reference no: EM131385942

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