Draw a plot of the target impedance versus frequency

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Reference no: EM131184718

A large microprocessor draws a total transient current of 10 A from a 3.3-V supply. The logic has a rise/fall time of 1 ns. It is desirable to limit the V_cc-to-ground noise voltage peaks to 250 mV, and each decoupling capacitor has 5 nH of inductance in series with it. The decoupling will be done with a multiplicity of equal value capacitors, and should be effective at all frequencies above 20 MHz.

a. Draw a plot of the target impedance versus frequency.

b. What is the minimum number of decoupling capacitors required?

c. What is the minimum value for each of the individual decoupling capacitors?

d. Could larger value capacitors be used just as effectively?

Reference no: EM131184718

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