Draw a block diagram for the synchronous receiver

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Reference no: EM131367457

The operation of a synchronous receiver is somewhat similar to the UART receiver discussed in Section 11.3, except both data (RxD) and a data clock (Dclk) are transmitted so there is no need to synchronize data with a local clock, and no start and stop bits are required. As shown below, when 8 bits of data are transmitted, the clock is actually active for nine clock times and then it becomes inactive. On the first eight clocks data is shifted into the receive shift register (RSR), and on the ninth clock, the data is transferred to the receive data register (RDR) and the RDRF flag is set.

(a) Draw a block diagram for the synchronous receiver, including a counter. (Note: A state machine is not necessary, but generation of control signals Load and Shift is required.)

(b) Write synthesizable VHDL code that corresponds to (a). Signals Load and Shift should appear explicitly in your code.

Reference no: EM131367457

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