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Name four of the six causes of declaring a frame relay frame invalid ? How are the FECN and BECN bits used? Distinguish between them. (Hint: Use direction of transmission) ? Discuss the use of the DE bit. Under what circumstances will the network change a DE bit setting? What are the three possible ways of handling billing on frame relay?
Two transformers each rated 250-kVA, 11/2-kV and 50-Hz are connected in opendelta on both the primary and secondary.
The load of an industrial plant is 400 kVA at a power factor of 75 percent lagging. An additional motor load of 100 kW is needed. Find the new kilovoltampere load and power factor of the plant load if the motor to be added
It is desired to place the poles of a second order systemso that the time to the peak of the step response is 0.75 sec andso that the settling time (2% criterion) is 3 sec. Plot therequired pole location in the s plane . What are the required valu..
An M-bit thermometer code for the number k consists of k 1s in theleast significant bit positions and M-k 0s in the more significant bit positions. A binary-to-thermometer code converter has N inputs and 2N-1 outputs.
Beaver Corp preferred stock has a market price of $14.50. If it had a yearly dividend of $3.50, what is your expected rate of return if you purchase the stock at its market price?
Design an npn current mirror for this purpose. Neglect the base curents.
Design a circuit which provides 20 dB of gain. The 3dB filter points should be 50 HZ and 50 KHZ. Use a bipolar power supply (+/- 9V). Your circuit should be able to provide a minimum of 5 Watts of output power.
The sampling frequency in a DSP system is fs = 8khz kHz. A hold circuit is used after the DAC device. What is the percentage of distortion level at the frequency f= 3.4 kHz
At a point 0.5 m downstream from the leading edge, the local shear stress at the wall is 282 N/m2. The gas temperature at the wall is equal to standard sea level temperature. At this point, calculate the velocity gradient at the wall normal to the..
Use a 74LS283N Adder chip and a 74LS86N XOR chip. Simulate the circuit in Multisim and test enough input combinations that you are sure the circuit is working properly. Make sure you test in all theranges of numbers that are possible.
Design a 4-bit decrementer using Half-adders and inverters as building blocks. The circuits impleents A-1=S. Draw the circuit diagram. Hint: consider addtion of the 2s complement of -1 =1111. Begin with a 4-bit adder circuit constructed with 1-bit..
(The output generates the 2's complement of the input binary number) Show that the circuit can be constructed using Exclusive-OR gates. Can you predict what the output functions are for a 5-bit 2's complement
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