Reference no: EM13227190

Design an FSM controller (ManchesterEncodingFSM)and model it using the canonical VHDL format. You must convert a raw serial bit sequence or 0's and 1's (RawSerialIn_H) into an encoded version of that data in the Manchester format (ManchesterSerialOut_H). Manchester encoding introduces a signal transition in the middle of each bit-time cell that is transmitted, this helps the receiving station to recover the clock that defines the cell boundaries because there will always be a transition in the middle of the cell boundary.

A high serial data bit-cell logic value must be encoded into a positive going transition in the middle of the serial data bit-cell of the Manchester encoded output.

A low serial data bit-cell logic value must be encoded into a negative going transition in the middle of the serial data bit-cell of the Manchester encoded output.

When there are consecutive bits of the same value, the output must also be made to transition at the begining of the serial data bit-cell of the Manchester encoded output so that the output signal is at the correct level to make the desired transition in the middle of the bit-cell.

1) For this ManchesterEncodingFSM the clock (Clk_H) will need to run at a speed that is twice as fast as the clock that defines the boundaries of the RawSerialIn_H serial data bit cell this will allow the FSM to resolve or discriminate the middle of each raw data bit cell period.

2) In addition because your FSM will have to examine or sample each bit being received (in the RawSerialIn_H) before it can decide how to pre-set the level of the ManchesterSerialOut_H signal so as to introduce the transition desired at the middle of the output cell time, there will be an off-set or distance (in time) between the output-bit cell-time period and the input-bit cell-time period. This offset will have a duration of one-clock-cycle of the FSM clock or half cell-time duration. To minimize this delay or latency your machine should be a Mealy type FSM.

3) You can assume that the clock defining the transitions in the RawSerialIn_H signal is synchronized to the Clk_H signal used in the FSM.

4) In Manchester encoding a '1' is coded as a rising transition in the middle of the manchester data-cell, and a '0' is encoded as a falling transition in the middle of the manchester data-cell.