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You are a thermal design engineer and plan to design cooling solution for a computer chip. As a basic design, a chip (K_c=50W/m-K) is mounted in a dielectric substrate (K_s=5.0 W/m-k) and one surgace of the system is convectively cooled, while the remaining surfaces are well insulated from the surroundings. It is reasonably assumed that the system to be very long in the direction perpendicular to the paper, so it is a 2D problem. Under steady state, electric power dissipation in the chip provides for uniform volumetric heating at a rate of q_dot=1.5x10^7 W/m^3. You are limited to forced air convection cooling with h=250 W/m^2-K and T_surr=40 Degrees Celsius. However the chip should not be allowed to rise above 85 degrease Celsius.
a) Solve for the temperature distribution within the chip and diateletect mount using finite-difference method. A grid spacing of 3mm is suggested. (Note that a symmetry condition exists.) Provide all discrete nodal equations (one for each different kind of node), and show their dedications.
b) Create a T-x plot for each row of nodal network (in one plot). Check if the package meets the industrial requirements (max temp of 85 degrees Celsius), you will find that the temperatures within the chip easily rise higher than the requirement.
Package Design Brief: Assume you are the packaging engineer for a large consumer products company. In this company, the Packaging Design Briefs are initiated by the marketing group and forwarded to the Package Engineering group.
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