Reference no: EM131049719

For the each of the following sequence of instructions use the abstract pipelined datapath.

Code 1:

lw $7, 0($1)
sub $7, $3, $7
add $3, $7, $3
sw $7, 0($3)

Code 2:

lw $2, 0($3) # Assume that this is a valid instruction in your datapath

add $3, $2, $4
sub $1, $3, $4
add $1, $5, $3
sw $5, 8($6)

(a) Label the bubbles caused by stalls. (Note you should not need more than 16 clock cycles)

(b) If possible, eliminate all of the bubbles caused by the instruction sequence in part (a) by reordering the instruction sequence and/or by adding bypass paths to the basic, standard pipeline diagram. Give the reordered instruction sequence.

(c) Add bypass hardware (data forwarding paths(s) into the hardware datapath) and reorder the code sequence to eliminate all the stalls for Code 2.

(d) Assume that the register writes occur in the SECOND half of the clock cycle and reads occur in the rst half. Add a bypass (data forwarding path into the hardware datapath) to eliminate all stalls from the Code 2 sequence in Part (a).