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Design a cache with cache size of one hundred twenty-eight K bytes, block (line) size of eight words, and word size of four bytes. Consider a computer with sixty-four-bit physical address. The cache is addressed byphysical address.
i) Determine the tag array size (in bytes) for three cache implementations (direct-mapped, 16-way set-associative, and fully associative).
ii) Using the tag array sizes computed in (i), compare the percentage overhead of different cachedesigns. In other words, compute the percentage of the tag array compared to the originalcache design (one hundred twenty-eight K), and identify the best, moderate and worst cache implementations interms of tag area overhead.
iii) Why would anyone use the implementation you identified in (ii) with worst area (tag array)overhead? In other words, identify a scenario when a designer will use the cacheimplementation that you identified in (ii) with worst area overhead.
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