Reference no: EM13164892

You are tasked with designing a 24 CPU multiprocessor chip to compete with Intel PHI at a lower price point. Each core will run at 2 GHz and have a 32Kb L1 cache, 50ps access (per word), 8 word blocks, 4-way associative, write-through, 1% miss ratio There is a 6Mb L2 cache, 1ns access 32 word blocks, 4-way associative, write-back, 20% miss ratio 16.7% (1/6) dirty. The L2 cache is shared between all 24 cores, and has 3 connection buses, 2 words wide each multiplexed to 8 cores. RAM is 1600MHz DDR3 memory, access 8 words wide (pipelined 8 words per memory cycle on the memory bus). Assume 4 instructions per cycle per core, and 25% of instructions are 3 address floating point, and that floating point data read/write and instruction reads represent all memory access. (a) What is the peak bandwidth between memory and multiprocessor required to support computation on your chip? (b) What is the peak bandwidth between L1 and L2? (c) What is the peak bandwidth between L2 and RAM? (d) Under the given conditions, is the chip you are designing a reasonable proposition? (Assume that an average load would use some fraction of peak bandwidth). If your answer is "no", What would you improve to make this chip viable? (e) Would it make sense to make your chip available as a card on the PCIe bus (like a GPU)? (Why or why not)