Design values of w-l of the set and clock nmos transistors

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Reference no: EM13271821

A CMOS clocked SR flip-flop uses a technology with unCox = 100 uA/V^2, upCox = 25 uA/V^2, VDD = 2.5V, Vtn = -Vtp = 0.5V and the total capacitance at the output nodes equals 15fF. The inverter threshold voltage VM = 2.5V. The latch NMOS transistors Q1 and Q3 have (W/L)n = 1 um/0.5 um and the PMOS transistors Q2 and Q4 have (W/L)p = 2 um/0.5 um.

1. sketch the circuit showing SET, RESET, clock input and Q and Q' outputs.

2. propose for your design values of W/L of the SET and clock NMOS transistors and determine the associated SET time. Be aware that SET time will depend on your design and hence the optimum design is better rewarded.

Reference no: EM13271821

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