Design the saturated load inverter circuit

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Reference no: EM131228107

(a) Design the saturated load inverter circuit in Figure

(a) such that the power dissipation is 0.30 mW and the output voltage is 0.08 V for v_I = 1.4 V. The circuit is biased at V_DD = 1.8 V and the transistor threshold voltage of each transistor is V_TNO = 0.4 V.

(b) Using the results of part (a), find the range of input voltage such that the driver transistor is biased in the saturation region.

2425_Figure 6.jpg

Reference no: EM131228107

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