Design in the fpga development board

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Reference no: EM131176894

Blinking Light Solve exercise 9.2 using SystemVerilog instead of VHDL.

Exercise 2 in Chapter 9

Blinking Light This exercise concerns the blinking light FSM of figure 8.12c.

(a) Which of the two timer control strategies (#1, section 8.5.2, or #2, section 8.5.3), if any, can be adopted in the implementation of this FSM?

(b) Implement it using VHDL. Check whether the number of DFFs inferred by the compiler matches the prediction made in section 8.11.1 for each encoding option (sequential, Gray, Johnson, and one-hot). Recall that the predictions must be adjusted in case the clock frequency is different from 50 MHz.

(c) Physically test your design in the FPGA development board. Use two switches to produce rst and ena and use an LED to display the output.

Reference no: EM131176894

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