Design for mos inverter using a depletion-type transistor

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Reference no: EM13261597

Create the layout design for MOS inverter using a depletion-type transistor with VTL = -0.3V and an enhancement-type device with VTO = 0.5V such that tPLH is less than or equal to 15ns and tPHL is less than or equal to 1ns with CL = 1pF. VDD = 2.5V , tox = 10nm and 2X = 700nm .

Reference no: EM13261597

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