Design encoder using karnaugh maps to minimize logic element

Reference no: EM131023613

Figure P7.87 shows the functional diagram of an electronic die that can be used in games of chance. The system contains a high speed clock, a push-button momentary contact switch that returns to the upper (logic 1) position when released, and a counter that counts through the cycle of states: 001, 010, 011, 100, 101, 110 (i.e., the binary equivalents of the number of spots on the various sides of the die). Q3 is the most significant bit (MSB), and Q1 is the least significant bit (LSB). The system has a display consisting of seven light-emitting diodes (LED), each of which lights when logic 1 is applied to it. The encoder is a combinatorial logic circuit that translates the state of the counter into the logic signals needed by the display. Each time the switch is depressed, the counter operates, stopping in a random state when the switch is released.

a. Use JK flip- flops having asynchronous preset and clear inputs to draw the detailed diagram of the counter.

b. Design the encoder, using Karnaugh maps to minimize the logic elements needed to produce each of the seven output signals.

Reference no: EM131023613

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