Reference no: EM131854270

Learning objectives

Upon successful completion of this coursework, the student is expected to:

Be aware of the diversity in Instruction Set Architectures and the issues architects consider when designing new ISAs.

Become familiar with assembly language programming and its relationship to high-level languages, both in theory and practice.
Understand the details of CPU and memory organization.

Understand the operation of the CPU Fetch-Decode-Execute cycle.

Appreciate the technique of software simulation to test designs, such as Instruction Set Architectures.
Be familiar with information units (bits, bytes, words) and number systems (binary, decimal, hexadecimal).

Description / Scenario

As a computer architect, you are given the task to design a simplified computer with its own RISC Instruction Set Architecture. Having this task completed, your next step is to test the new ISA by writing an interpreter that simulates programs in this language.

The designed computer has a 2 -byte word size (hence, the term "word" is redefined in this project to mean 2 rather than 4 bytes), is equipped with a total of 16 general purpose registers of size one word, numbered 0 to 15, and a small main memory (RAM) of 256 words. The computer CPU also contains one program counter (PC) register and one instruction register (IR) where the current instruction is temporarily stored. Given these characteristics, the new ISA is a simplified version of MIPS, which consists of fixed-size 16-bit instructions, i.e. they occupy one word of the memory. More details in attached file.

Task 1

Manually write machine language programs in the newly-designed ISA for the following:

a) Read a positive number n from the keyboard and compute and display its partial sum, calculated by n(n+1)/2

b) Read a positive number from the keyboard and compute and display the smallest power of two, which is larger than the read number. E.g. for 1000, the program should produce 1024.

c) Read a series of integer numbers, and determine and display the largest number. The first number read indicates how many numbers should be processed.

Associate each line of the program with a short comment or explanation.

Task 2

In this task you are going to develop your own interpreter of the new ISA, in your programming language of choice. This will turn the machine into a simulator of the newly- designed computer system and test its operation, before having to invest huge sums of money in the manufacture of its hardware chips!

Although students have the choice of command-line versus graphical interface for the ISA simulator, they are recommended to keep it simple with a Command Line Interface (CLI). The simulator begins its execution by prompting the user to enter the program one hexadecimal line (word) at a time for each memory address, starting from 00. User signals the end of the program by a special value, e.g. -11111. As the program is entered, the simulator loads it into the memory.

The memory can be represented with a one- dimensional array of 256 integer elements (since instructions as well as data are numbers). In this design the memory is word-addressed rather than byte-addressed. If the second were the case, the simulator would be slightly more complex by accessing memory at even-number locations, and PC would have to be incremented by 2 each time.

Next, the simulator executes the program. Execution begins with the instruction in location 00 and continues sequentially, unless a transfer of control instruction is encountered.

CPU registers (16 general, 1 PC and 1 IR) will have to be stored in separate variables. Also use a variable to hold the op-code of the instruction currently being executed. Do not execute instructions directly from memory. Rather, "fetch" the next instruction to be performed (incrementing PC as appropriate) from the memory array to the IR. Then "pick off" the leftmost hexadecimal digit and place it in op-code variable. Decode the instruction based on the op-code (e.g. through a "switch" structure) and based on the instruction type read the rest of the fields in separate variables. Keep in mind that when the simulated computer begins execution, the registers are all initialized to zero.

When the assembly program completes execution, the name and contents of each register, as well as the contents of memory should be displayed ("computer dump"). In order to keep the output size manageable, do not display all 256 words, but say the first 100 words in memory.

At this point, you should be able to implement the new ISA simulator and run each of the assembly programs in Task 1.

You are encouraged to extend the simulator to check for various types of errors. For example, during the program-loading phase, each hexadecimal number that is entered must be in the range -ffff to +ffff.

During the execution phase, the simulator should check for various types of errors, such as detecting an instruction with invalid op-code, or outside the range (e.g. negative), register overflows and underflows during arithmetic instructions, etc. Other types of execution errors could be attempts to divide by zero. Whenever errors are encountered, the simulator should terminate with the display of the appropriate message, as well as a full computer dump. This treatment will help the user debug the assembly programs.

The student should be careful to make the necessary conversions between hexadecimal and decimal number systems and not confuse the two. In Java, the library class Integer provides methods that parse a hexadecimal string to an integer, and vice versa, output an integer as a hexadecimal string.

Attachment:- Handout.rar