Reference no: EM133119881

7ENT1112 Smart Embedded Systems Engineering - University of Hertfordshire

OBJECTIVE
To design and simulate a 3-input NAND gate in CMOS logic and perform raise/fall delays analysis using Multisim.

BACKGROUND INFORMATION
After the lab session, you will also need to write a report plus some additional information and analysis as described in the Assignment Briefing Sheet.

Static power due to sub-threshold leakage is highly dependent on the subthreshold voltage of the devices used to implement the logic gates. Using high Vth devices (VTH) can lead to a dramatic improvement in the leakage current, but has the undesirable effect of increasing the propagation delay of the gate. The idea of Multi-threshold CMOS is to allow gates to operate at low Vth delay values, when in "active" mode, but dissipate low leakage power when in "standby" mode.

For this exercise you will be using a 45nm bulk CMOS technology for your simulations. The SPICE parameter values are as follows:
• 45nm process technology
• Vdd = 1.0V
• Low-Vth-N = 0.22, Low Vth-P = - 0.17 (approx.)
• High-Vth-N = 0.35, High Vth-P = -0.33 (approx.)

TASKS

Part 1: Transistor level 3-input NAND with low-Vth (VTL) and high- Vth (VTH) devices

Complete the following without a load capacitor

1. Design a simple 3-input NAND gate in CMOS logic. Note you will need to design your NAND gate from scratch, at the transistor level. Use low-Vth (VTL) devices. Assume a minimum sized transistor with Wn/Ln = Wp/Lp =3, where Ln = Lp = 50nm (allowing for Leff = 45nm) and μn/μp =2.

(Hint: Use Virtual transistors, click on ‘Edit model to change Vth (VTO/threshold voltage)

2. Carry out a theoretical analysis on paper first, describe and explain the input patterns that produce the worst-case rise/fall delays.

3. Simulate and demonstrate correct logical and electrical behaviour with input patterns that produce worst-case rise/fall delays from your paper analysis. Report the worst- case rise/fall delays.

4. Describe and explain the input pattern that dissipates the highest dynamic current (i.e. the one that has the highest drain current Id when the output switches). Then use Multisim to obtain the average dynamic power in your circuit. In this case, average current is measured during the rise time and fall time (0.1*Vdd to 0.9*Vdd).

5. Repeat steps 1-4 for a 3-input NAND gate implemented with high- Vth (VTH) devices.

Part 2: Active and Standby Mode

6. Starting with the low-Vth NAND gate, add sleep transistors to the pull up and pull down networks using high-Vth (VTH) devices for the sleep transistors. Note that insertion of the sleep transistors will require careful sizing so that delay is minimally affected and leakage is minimized.

7. With the gate in active mode (i.e., sleep transistors are on), measure the following:
a. Propagation delay for all input patterns (from the 50% Vdd point of the input signal to the 50% Vdd point of the output signal).
b. Worst case dynamic power.
c. Leakage current using input assignments that minimize leakage.

8. Repeat part 7 with the gate in standby mode (i.e., with the sleep transistors in the off state). Note that parts (a) and (b) do not necessarily make sense when operated in standby mode, but the waveforms and power values are interesting to observe.

Attachment:- Embedded Systems Engineering.rar