Reference no: EM13500580

Design an 8 GB memory subsystem for a desktop PC system employing DDR3 SDRAM  chips on a standard DIMM with ECC and 72 data lines (for data and ECC). The SDRAM chips use a 1KB page size, 8 banks, and tRCD = CL. The DIMMs employed are 4GB PC3-19200 with timing (10-12-12-31) a) How many SDRAMs are on the DIMM if 512M x 8 SDRAMs are used?
b) How many ranks would there be per DIMM?
c) How many ranks are there in the memory system?
d) What would be the impact of using 256M x 16 SDRAMs on the memory organization? Are there any disadvantages?
e) What is the maximum bandwidth of one DIMM?
f) How much time (in ns) is required from the presentation of the activate command until the end of the cycle during which the last bytes of data are transferred? Assume the bank is precharged.
g) Assuming we could always arrange it so that the bytes we want from memory are
among the first 8 bytes of the burst, how much faster on average can we expect to get the  data? Assume that the memory  controller implements a closed-page policy, pre-charging after each access to a bank. Give your answer as a percentage improvement over not  using this technique.

h) What is the ratio of the amount of time it will take to complete a read from a location  requiring a bank activate command (page empty) versus a read from a location in an already open page (page hit)?
i) Assume a scenario in which the memory controller implements an open page policy. If  a long sequence of memory references results in all page misses, what bandwidth can we  expect?
j) How does the result in (i) above compare with the maximum theoretical maximum bandwidth of the PC3-19200 DIMM?