Design a watchdog timer that takes a clock

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Reference no: EM133177926

Question: Design a watchdog timer that takes a clock (with a clock frequency of 2 KHz) and a reset pin as its input and one signal S1as its output. S1 goes high when the timer exceeds 35 msec.

When S1 is high, the system resets immediately (the process is at fault). Assume that under normal operation, a processor resets the timer every 30 msec.

Reference no: EM133177926

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