Design a mealy finite state machine

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Reference no: EM131387548

(Design Process) Design a Mealy finite state machine with input X and output Z. The output Z should be asserted for one clock cycle whenever the sequence ... 0111 or ... 1000 has been input on X. The patterns may overlap. For example, X = . . . 0000111000 . . . should generate the output stream Y= . . . 0000001001 ... .

(a) Complete the state diagram for the sequence detector, with-out concern for state minimization.

(b) Complete the state table for the state diagram derived in part (a).

(d) Use the state assignment guidelines to obtain a good state assignment for the reduced state machine of part (c). Justify your method in terms of the high-, medium-, and low-priority assignment guidelines.

(e) Implement your encoded, reduced state table and show all the minimized logic equations for the next state and outputs.

(f) Describe your finite state machine in a Verilog description.

Reference no: EM131387548

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