Reference no: EM131217435

Write the given digital circuit lab assignment.

Design Problem -

1. Design a full-adder circuit which adds three binary digits x_i, y_i and carry in c_i. Your circuit should compute the sum out s_i, and carry out c_i as shown in Figure 1.

Use any logic gate to design this circuit.

Write the Boolean equation for this circuit and give the corresponding gate level schematic diagram for your circuit.

Draw in laboratory notebook.

Implement the circuit in structural Verilog and simulate it in ISIM.

Use a test bench and top level circuit. After proving that your unit under test is properly designed, synthesize the circuit in the Xilinx environment. Use the appropriate switches and LEDs to prove that your circuit works properly

1) show code and simulation results ;

2) show board test results

2. Now create full-adder circuit again using a behavioral Verilog. Again simulate the circuit and implement it on the FPGA boards.

1) show code and simulation results ;

2) show board test results

3. You have been asked to design an arithmetic incrementer/decrementer circuit. Your circuit will receive a 3-bit binary number (A) as input to produce an output which is either A+1 or A-1 depending upon the command input (ID). That is, your circuit works as an incrementer if the command ID=0 or a decrementer if ID=1.

Use any logic gate to design this circuit. Give a gate level schematic diagram for your circuit. Draw this in pre-lab report.

Implement the circuit in structural Verilog and simulate it in ISIM.

Use a test bench and top level circuit. After proving that your unit under test is properly designed, synthesize the circuit in the Xilinx environment. Use the appropriate switches and LEDs to prove that your circuit works properly to the TA or instructor.

Note: a solution has been supplied to help you with the 3-bit design. 1) show code and simulation results ; 2) show board test results.