Design a dtack circuit that will generate the correct number

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Reference no: EM13208606

Design a block of memory which is 512K x 8 bits using memory chips which are 128K x 8 bits. Assume that the chips are ROM with Chip Enable inputs, and Output Enable inputs. How many address inputs do the individual chips have? How many total address lines are needed to decode the entire 512K? Show the decoder and indicate which address lines are used as its inputs and show how its outputs are to be used. Assume that the microprocessor has a 24-bit address bus and design decoding logic to place your memory block at a base address of 0xD80000. Assume the processor has a clock period of 5ns and the memory chips' access time is 58 ns. Design a DTACK circuit that will generate the correct number of wait states.

Reference no: EM13208606

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