Reference no: EM131205843
EE Design Project - 4-Bit Mini-CPU
Problem Statement: You are to design a 4-bit mini-CPU which will perform 6 instructions: Compare, Add, Subtract, AND, OR, and NOT. That is, it can compare two 4-bit numbers, add two numbers, subtract two numbers, AND two numbers, OR two numbers, and take the 1's complement of a single number. The CPU does only fixed-point number manipulations, so you do not have to worry about floating point numbers.
Both data and instructions are loaded from a single bus which comes from computer memory. You do not have to worry about the other end of that bus. The system operates on a 3-bit counter that counts modulo-8, driven by a clock that is supplied. On count 1, the 4-bit instruction is loaded from the bus. On count 3, the first operand is loaded, and the second operand is loaded on count 4. The result is loaded into the "result register" on count 7. Count 0 is a pulse at the beginning of the cycle that signals that data on the output bus is valid. The output of this register is all you are responsible for. How the resulting data is used is taken care of by another designer. All you must do is computer the result and generate the "Data Valid +" signal at clock count 0.
There is a reset that starts up your system, and then the clock starts and runs continuously. Since your circuit is based on an 8-count cycle after the clock starts, you must provide a modulo-8 counter (3-bit binary counter). The following signal inputs are given:
1. Clock In: A 50/50 pulse input that begins after Reset- and runs continuously.
2. Reset-: A negative-going signal that resets the system at startup before clock start (clears all registers).
3. Instruction/Data Bus: Four data lines, W-Z (W = MSB), on which data and instructions appear as noted above: The Instruction Word is valid on lines W-Z on count 1 of the clock, Operand 1 is valid on count 3, and Operand 2 is valid on count 4.
4. Note that in the instruction word, W is the most significant bit. The Op codes for the instructions are as follows: Compare = 0x2, Add = 0x4, SUB = 0x6, AND = 0x7, OR = 0xa, and NOT = 0xe. These Op codes must be decoded so the correct answer will be loaded in the result register.
Your job is to design the following:
1. Build a 3-bit counter that counts modulo-8 continuously. It is reset only at startup with Reset-.
2. Build three 4-bit registers to hold the Instruction Word that is transmitted on count 1, Operand 1 that is transmitted on count 3, and Operand 2 that is true on count 4.
3. You may use a 4-bit adder chip instead of designing the adder from smaller logic pieces. Note that using the adder chip, you may add, subtract, and compare (all 3!), so you do not have to build a separate subtractor or comparator unit.
4. Note that the comparator should be designed only to show equal or not equal. It is not designed to show which operand in a compare is larger.
5. Design a 4-bit bit inverter for the NOT circuit. Note: In the case of the NOT instruction, only Operand 1 is used.
6. Design 4-bit AND and OR circuits to perform those operations.
7. Design a 5-bit register to hold the sum and carry out (overflow) of the adder (outputs V'-Z'), as well as the result of the other functions. Note that V' is used to hold the Carry Out bit for Add and Subtract instructions and the compare status bit when a compare is executed. For Operands 1 and 2 equal, V' = 1, for Operands 1 and 2 NOT equal, V' = 0. NOTE! When using the adder as a comparator, be certain to disable the carry bit, as you are using V' as the compare valid bit.
8. Build a timer circuit that detects counts 0, 1, 3, 4, and 7 and generates the appropriate signals.
9. Build a MUX that chooses the correct result by decoding the Op codes 2, 4, 6, 7, 0xa, and 0xe. This will allow storage of the correct result in the Output Register. Also, send the control lines that activate the six functions out of the system as well (just as "Data Valid +" is output), so that the receiving circuits will have a signal as to what operation is performed.
Attachment:- Assignment.rar