Design a 2-way set-associative cache with 16-byte cache line

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Reference no: EM13255019

1. Design a 2-way set-associative cache with 16-byte cache lines and a data capacity of 16 kB (kilobytes).

2. Assume a 1-bit valid field, and find the total size in bytes of the cache that you designed in Problem 1, including the valid, tag and data bits.

3. This problem explores the performance consequences of having only a single level of cache in a modern processor with 40 ns DRAM column access time and a clock period of 400 ps (clock frequency 2.5 GHz). You are given the following data: A particular processor with separate data and instruction caches would have a CPI of 1.00 if all data and instructions were instantly available. 20% of the instructions executed are reads and 20% are writes. The penalty for main memory access is 100 clock periods for both data and instructions. The probability of an instruction cache miss is 2%. The probability of a data cache read miss is 5%. The data cache has a write-back, write-allocate organization. Find the resulting CPI including cache miss penalties.

Reference no: EM13255019

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