Describe in vhdl the circuit k use structural architecture

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A circuit computes the product of two numbers, a 4-bit A[3..0]=A3A2A1A0 and a 3-bit B[2..0]=B2B1B0 which they appear in input. The output P[6..0]=P6P5P4P3P2P1P0 represents the answer (e.g. if A=1011 and B=101 then P=0110111).

Using a 4-bit Full Adder as the basic structural component, and another one type of gate, describe in VHDL the circuit K. Use structural architecture and channels for the inputs and the output of the circuit. (First of all you will have to implement the 4-bit Full Adder in VHDL by using any description type of the architecture. As inputs take the channels X[3..0] and Y[3..0], and as outputs the sum Z[3..0], in channel form and the carry output Cout.)

Reference no: EM13279682

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