Reference no: EM133232467
For this problem you are given a cell library consisting of full adders and two-input Boolean logic gates (i.e., AND, OR, INVERT, etc.).
a. Design an N-bit two's complement subtracter using a minimal number of Boolean logic gates. The result of this process should be a diagram in the spirit of Figure 11.5 (J. M. Rabaey, et al., Digital Integrated Circuits, 2nd ed.). Specify the value of any required additional signals (e.g., Cin).
b. Express the delay of your design as a function of N, tcarry, tsum, and the Boolean gate delays (tand, tor, tinv, etc.).
4. Show how the arithmetic module in Figure below can be used as a comparator. Derive an expression for its propagation delay as a function of the number of bits.
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