Demonstrate your design respects the requirements

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Reference no: EM133393752

Question: Design and layout of NAND 3:

The specification you must meet with your design is that the worst-case switching delay must be less than 2ns when driving a load of 100fF. You must design both the P and N networks intelligently, which is to say that you must ensure that the values for τgc and τgd meet the timing requirement. Do not exceed the timing specification by more than a factor of 20%, i.e. your τgc and τgd values must be greater than 1.6ns, but do not need to be identical. You should calculate the width and length for each transistor. Draw the NAND3 circuit diagram, indicate the widths and lengths for each transistor and show your complete calculations to demonstrate your design respects the requirements.

Process parameters:

Kp' = 13 μA V-2;

KN' = 44 μA V-2;

L = 2.00 μm;

Cox = 9 x 10-4 pFμm-2;

Reference no: EM133393752

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