Define transferring data from any core to any other core

Assignment Help Basic Computer Science

Reference no: EM13761254

Q1: Design a system with 2 4-bit shift registers with a bus (single wire) connecting the two.

a) Design the system so that the endianness (bit order) is retained

b) Design where the endianness is reversed

Q2: Design a system which has an array of memory in registers, with 4 rows of words, with a word length of 16 bits. You can assume the existence of an 8-bit register as a primitive component you just draw as a box. (E.g. lecture 9 slide 26)

a) Design a system that will transfer data from any selected row into a shift register of the word size, preserving endianness.

b) Design a system that will transfer data from any selected row into a shift register of the word size that reverses byte ordering but not endianness

c) Design a system that will transfer data from any selected row that will transfer data into a shift register that reverses both byte order and endianness

Q3. Explain why loose timings on RAM memory might be useful in a multicore environment. If you know how to do a timing diagram that could be useful but you can also explain the concept. Assume that transferring data from any core to any other core could take at least one clock pulse.

Q4. Assume the speed of electricity in a copper wire is 2x10^8 m/s. Now assume you have a memory system with 3 levels of caches and main memory - hard disk, connected in the following way CPU - L1 -L2 -L3 - Main Memory - hard disk.

Assume that the fastest (L1) cache takes 0.5 ns per access from the CPU, the L2 cache 7ns from the L1, the L3 cache 40 ns from L2, RAM takes 160ns from L3, and a hard disk takes 2000 ns from RAM.

What is the maximum distance each of these components can be from the next one in the chain before they would need longer access times?

Just calculate how far electricity can travel in those access times (N.B. For physicists, ignore the concept of the speed of the wave versus speed of the electrons, for networking students, you can ignore nyquist and Shannon's theorems).

Q5. Compare the latency, single word, and 8 world read time of memory with the following properties, (I lifted this example from the 2 bestselling ddr4 memory kits on newegg.ca)

a) DDR4 - 2666 (PC4-21300) timings 16-18-18-35

DDR4 2400 (PC-19200) - timings 15-15-15-35

b) If you were to Improve the timings on this memory (e.g. reduce the timings to 14-16-16-35 and 13-13-13-35)how likely is it that you would be able to notice the performance improvement in a typical video game or regular office use scenario?

Reference no: EM13761254

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