Define the quiescent-idle response of the circuit

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Reference no: EM13228405

The circuit should be capable of dividing two binary numbers with decimal values as large as 10,000.

The circuit will have as inputs a minimum of two inputs; the binary equivalent of two decimal numbers of not greater than (10,000)10. The circuit will also produce a minimum of two outputs, the quotient and the remainder. This circuit should be simulated by verilogger or another program.

(Any kind of help would be very appreciated)

Define the required logic of the device

Design all components down to gate level

Define inputs and outputs

Create a flow chart outlining the logic implemented by your circuit

If a state machine is used, provide a state diagram

Define the quiescent (idle) response of the circuit

Define any "error" or "undefined" states or input combinations of the circuit

Generate a report for submission
Cover page
Problem Description
Description of Solution
Detailed design methodology

i.Why certain design choices were made

ii.What are the advantages of components of your design

iii.Simplified expressions created

iv.K-maps utilized

v.Work required to complete the design

Reference no: EM13228405

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