Define synthesizer architecture to provide desired signals

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Reference no: EM13227297

A military radio system operates at frequencies from 30 - 88 MHz with 25 kHz channel spacing. The receiver uses a 10.7 MHz IF. For cost, power, weight and size reasons, it is desirable to use a single clock oscillator that will provide the frequency reference for the synthesizer, as well as providing the clock for data.
The system must support data rates of 8, 16 and 32 kb/s, and it is desirable for it to provide data rates of 1.2, 2.4, 4.8, and 9.6 kb/s. The receiver will require a clock source that is 16 times the data rate so, for instance, to operate at 16 kb/s,the clock source would need to be 256 kb/s.
• Define the synthesizer architecture (reference frequency, divide ratios) to provide the desired signals with as few divider stages as possible and the lowest master clock frequency possible.

Reference no: EM13227297

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