Reference no: EM132249283

Fundamentals of Digital Systems Lab 5 - Layout Related Circuits: Alternative Circuit Descriptions: Reduced XOR Vectors

This lab will show you how to functionally verify your designs prior to synthesis. It will also will help you to learn how your VHDL description shapes the circuit layout that is derived during synthesis and place-and-route. You will need to modify your testbench, and you will need the below listed files.

• clock.vhd (VHDL folder)
• txt_util.vhd (VHDL folder)

For Lab #4, pay attention to how many XOR gates are required for each circuit description, and why. You will use this information for your next lab when we will synthesize all designs and look at the underlying architecture using XILINX tools.

1. Modify your Matlab Program and create input/output test vector files for the Reduced XOR vector functions if necessary. (Hint: if the bit-width of input/output are the same, and the description executes the same function, you can use your existing I/O files).

2. Copy and compile the Reduced XOR VHDL code shown in:

a. Listing 7.20 (Shared Vector Description).

b. Listing 7.21 (Compact Vector Description).

c. Listing 7.22 (Direct Tree Vector Description).

d. Listing 7.23 (Parallel-prefix Vector Description).

i. Create as many testbenches as necessary to simulate each listing.

ii. Compile all vhd files. Order is important. Compile the clock and txt_util vhd files, your VHDL entity files, and finally, the testbench files.

iii. Simulate all circuits [Listing 7.20 -- Listing 7.23].

iv. Sort your signals as per your lecture notes, and save the wave formats in .DO files.

v. Generate the data flow schematic for all designs, and save them (screen shots). Remember, the screen shots must be large enough to be useful. They should not contain extra content (like, your desktop). They must contain all items in design.

3. Place your vhd/do/mfiles/text files and screenshots into a zip file. Follow the naming conventions:

a. Your vhd entity files [LASTNAME_architecturename.vhd].

b. Your vhd tb files [TB_LASTNAME_entityname.vhd].

c. Your input.txt files [LASTNAME_entityname_INPUT.txt].

d. Your Expected_Output.txt files [LASTNAME_ entityname _EXP_OUTPUT.txt].

e. Your .mfiles [LASTNAME_Lab5_description.m].

f. Your do files. [LASTNAME_architecturename.do].

g. Your screenshots [LASTNAME_architecturename.jpg].

Your zip folder should begin with your last name and end with the Lab number.

Note - You will need to use MatLab and ModelSims. There are vhd files required for this project produce the hd/do/mfiles/text files and screenshots into a zip file.

Attachment:- Assignment Files.rar