Create and simulate a full adder assign pins to the design

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Reference no: EM13775721

Objectives

Upon completion of this laboratory exercise, you should be able to:

• Create and simulate a full adder, assign pins to the design, and test it on a CPLD circuit board.

• Use the full adder as a component in an 8-bit parallel binary adder.

• Create a hierarchical design, including components for full adders and seven-segment decoders.

• Design an overflow detector for use in a two's complement adder/subtractor.

1. The logic diagram for a full adder is shown in Figure. Use this diagram for a file.

1802_Full Adder Circuit.png

2. Save the full adder design file and use it to create a project in Quartus II. Compile the project.

3. Write a set of simulation criteria to verify the correctness of your design. Use the criteria to create a simulation for the full adder. Show the criteria and simulation to your instructor.

Reference no: EM13775721

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