Create a half adder module and testbench in verilog

Reference no: EM131232905

Assignment

1. Create a Half Adder module and testbench in Verilog. Show your output as a truth table.

2. Create a Full Adder using the Half Adder module, and a testbench for the Full Adder. Show your output as a truth table.

3. Simplify the following expression and then implement in Verilog.

A^-B^-C^-D^- + A^-B^-CD^- + AB^-C^-D^- + ABCD

4. Verify the DeMorgan's law for the following expression with Verilog.

A^-B = A^-+ B^-

Reference no: EM131232905

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Reviews

len1232905

10/7/2016 12:50:49 AM

You only need to send the code and the outputs in a word. In this assignment, you will code in Verilog. Submit a printed copy of your Verilog modules, testbenches, and results. Also, use the submit command on gl to submit your code.

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