Cputer architecture question 1 evaluate 0xf00 0x100

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Reference no: EM13347855

(Computer Architecture)

Question 1

Evaluate 0xF00 + 0x100 = ?

Express the answer in hex notation.

Question 2

Suppose integer 0x41FF is stored at word address 12 in a 32-bit little endian machine. What is the value in each byte location?

address

12

13

14

15

value





Question 3.

Suppose integer 0x41FF is stored at word address 12 in a 32-bit big endian machine. What is the value in each byte location?

address

12

13

14

15

value





Question 4.

Suppose integer -123 is stored at word address 12 in a 32-bit little endian machine in two's complement format. What is the value in each byte location?

address

12

13

14

15

value





Question 5.

Suppose that x and -x are 8-bit integers represented in two's complement format. Does  always implies . If not, give a counter-example.

Question 6.

Suppose that x and -x are 8-bit integers represented in two's complement format. Does  always implies . If not, give a counter-example.

Question 7.

A -to-1 multiplexer, with n control bits and  input lines can be used to implement any binary function with (n+1) input variable. Suppose you have the following 4-to-1 (4 way) multiplexer

How can you connect the input lines D0, D1, D2, D3 above so that the mux4 above implement the majority function M(s0, s1, s2)?

Hint: Each input line can be connected to either 0, 1, s2 or . M(s0, s1, s2) = 1 if two or more input lines are of bit value '1'. Otherwise,  M(s0, s1, s2) = 0.

Question 8.

Provide a HCL representation of the above majority function. Please use the format of HCL representation in the textbook or the slides.

Question 9.

Consider the following un-pipelined computation system. The computation in the combinational logic takes 400 ps to complete and the storing the result to the register takes 20ps. What is the throughput of the system? What is the delay of the system?

Question 10.

Suppose the computational logic in the above block can be partitioned into k pipeline stages, each having a delay of 400/k ps. If k = 4, what is the throughput of the system and what is the delay of the system? If k approaches infinity, what is the throughput of the system and what is the delay of the system?

Reference no: EM13347855

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