Convert the program to a recirculating shift register

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Reference no: EM131391159

The VHDL program in Figure 13-9(a) is the implementation of a parallel-load, shift-right shift register.

(a) Download the files shift_b.vhd and shift_b.vwf. Save these files with the new name prob_c13_2.vhd and prob_c13_2.vwf.

(b) Create a new project and compile and simulate this program. (Remember, the Entity name must be changed to the new name in all three locations before attempting to compile.)

(d) Run the simulation demonstrating the shifting sequence q3-to-q2-toq1-to-q0-to-q3, etc.

(e) Download your design of part (c) to an FPGA IC. Discuss your observations of the q output LEDs with your instructor as you demonstrate the recirculating shift-right operation. Use a debounced switch for n_cp. (The DE-2 has debounced pushbuttons.)

Reference no: EM131391159

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