Reference no: EM131248025

Consider the instruction sequence:

xor       $2,$0,$3
slt        $5,$2,$4
add      $11,$5,$11
sllv      $6,$11,$12
lw       $8,0x800($2)

sub      $2,$6,$8

1.) Assume that the pipeline system employs a hazard detection unit but no data forwarding unit and that register reads occur in the second half of the clock cycle while register writes occur in the first half of the clock cycle. If the xor instruction is fetched in clock cycle 1, during which clock cycle would the bolded lw instruction complete its write-back stage?

2.) Suppose that the same instruction sequence is executed again but with a data forwarding unit included.  If the xor instruction is fetched in clock cycle 1, during which clock cycle would the bolded lw instruction now complete its write-back stage?