Consider a cpu that implements four parallel

Reference no: EM13168623

Consider a CPU that implements four parallel fetch-execute pipelines for superscalar processing. Show the performance improvement over scalar pipeline processing and no-pipeline processing, assuming an instruction cycle similar to figure 4.1 in the commentary, i.e.:

a one clock cycle fetch
a one clock cycle decode
a two clock cycle execute

and a 60 instruction sequence:

No pipelining would require __?__ clock cycles:

A scalar pipeline would require __?__ clock cycles:

A superscalar pipeline with four parallel units would require __?___ clock cycles:

Reference no: EM13168623

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