Reference no: EM133781042

Question: In the single cycle CPU design it is necessary to have two memories, one for instructions and one for data. Now, you are asked to modify the single cycle CPU so that instructions and data can share the same memory.

Since arithmetic (R-R), branch (BEQ) and jump instructions do not access data, they can still complete in one cycle (since they access the memory only once). However, loads (LW) and stores (SW) must take two cycles. In the first cycle, the instruction is fetched and decoded, and the address is computed in the ALU; in the second cycle, the memory is accessed and, in the case of load, the returned value is stored in register.

The proposed data path is shown on the last page of the exam (you can tear off for convenience). For the second cycle of loads, we must buffer the memory address and the destination register address obtained in the first cycle. For this purpose, two registers, MemData@ (32 bits) and rt_buf (5 bits) have been added. Additionally, to handle stores, we must also buffer the value to store. For this purpose, a 32-bit register MemData has been added. Since these three registers are clocked in every cycle, they do not need any control point.

The control unit must be sequential. So, in effect, we now have a multi-cycle CPU. The state diagram for the controller has three states, 1, 2, and 3 and is shown in Figure 1 below. All instructions are fetched and decoded (including fetching the registers) in State 1. R-R, JUMP or BEQ instructions are also executed in State 1. A LW instruction is executed in State 2 and a SW instruction is executed in State 3.

Please complete the design by specifying the values of the control points using 0, 1 or X (don't care) in tables 1, 2, and 3 respectively. Make sure you identify all the don't care's since they simplify the control circuit. Some examples of the notation to use are shown in the tables. Control points may depend not only on the state, but also on the opcode.