CMPS 3023 Logic Design Assignment

Assignment Help Electrical Engineering

Reference no: EM132859196

CMPS 3023 Logic Design - MSU Texas

Project Assignment

This project is to be performed either individually or by a group of at most 3 students. Use the VHDL compiler or the Quartus schematics drawing tool to design an application specific integrated circuit implementing the MCA-4 microcomputer (Meaningless Computer Architecture with 4 bits) in accordance with the following specifications.

For this project, you are to design and simulate a 4-bit processor that will execute the given instruction set.

Mnemonic	Action	7	6	5	4	3	2	1	0
LD	Load value to Rr (r Î {0,1})	0	0	0	r	Value
AD	Add R0 to R1 resulting R2	0	0	1
AN	Logical product of R0 and R1 resulting R2	0	1	0
OR	Logical or of R0 and R1 resulting R2	0	1	1
MV	Move R2 to Rr	1	0	0	r
SB	Subtract R0 from R1 resulting R2	1	0	1
DS	Displays the contents of Rr (r Î {0,1})	1	1	0	r
NOT	Inverts the value of Rr (r Î {0,1}) resulting R2	1	1	1	r

The block diagram of the MCA-4 computer is shown next. The machine has 9 input signals: 8 for the instruction, and one for activation (clock). The activation signals should enable the circuit when it has value ZERO. When the activation signal is 1 nothing should happen. The MCA-4 has 7 output signals that control a 7-segment display (a value "0" lights a segment, while a value "1" switches it off). Register 2 must be displayed all time, unless a display command for register 1 is executed.

Project report:

Use computer word processing and drawing tools of your choice to generate your report. It must consist of the following items:

1. Block diagram of the circuit implementation (show major components like registers, logic units, connections, etc.).
3. Printout of the VHDL code or circuit schematics used to implement the design.
4. Printout of the simulation of all instructions (working or not)
5. Report on the behavior of the design when implemented in the test board (FPGA) if time allows

E-mail files or use D2L dropbox to turn in the VHDL or the schematics file (.vhd and .bfd). Do not turn in any other file. Your project is due on April 23, 2021. You must code/draw your VHDL/schematics using the same variable names as shown in the diagram above (a and x are vectors) - there will be a deduction of 20 points if the variables have different names, even if the circuit works.

You need to start working NOW!!!! Anything that you try to do in the last week before the due date will not work. Time is an important factor in this project. If your project does not work or you cannot justify why it does not work then your grade will be zero. Acceptable justifications are software limitations only and in this case you must show you had every component defined and tested and only the experiment failed.
Example of source code for the MCA-4: LD R1,9
LD R0,3
AD R1 MV R1 OR AN
NOT R1

Attachment:- Logic Design.rar

Reference no: EM132859196

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