Reference no: EM133199139

Introduction - The purpose of this essay is to assess the module learning outcomes through an extended discussion of concepts, approaches and design flows in digital design. Part 1 looks into the basics in interfacing digital systems with the real world and Part 2 is a Design Challenge. This is guided using a number of essay topics.

Part 1

Your essay must address the following topics:

(a) In 150 words or less, justify using VHDL for interfacing with analogue-to-digital converters (ADCs) and digital-to-analogue converters (DACs). In your answer, detail current digital design challenges and how VHDL solves them.

(b) In 150 words or less, describe the difference between absolute accuracy and relative accuracy for fixed point numbers using equations. Explain each of these terms and why they are important.

(c) In 200 words or less, calculate the minimum number of bits to represent temperatures between -40 and 80 degrees C at 0.01 degrees C precision, using a fixed-point number system and a scaled number. Show your working and discuss where a fixed-number system vs a scaled one could be useful in processing the values.

(d) An ADC interface is connected to measure an IQ (complex number) system using the input and output format from Part (c) to perform a power measurement. The required calculation is:

P(dBm) = 10 log (10 × (I² + Q²))

(i) Draw a block diagram showing the main VHDL entity blocks and number system signals to perform the above power calculation.

(ii) In 150 words or less, explain how each block could be implemented in VHDL and improvements to ensure synchronicity.

Part 2 - Interfaces with the real world require debugging to confirm operation in and during manufacture and to give users internal checkpoints. These interfaces are often seen as a security problem, providing ‘backdoors' to a manufacturers internal IP. When working with combinational and synchronous circuits, there are trade-offs between implementation styles.

(a) Take an existing design of the MIPS processor and draw what major blocks need to be added to incorporate a ‘debug mode' in the processor design. Describe each new block and make justifications for your choices. Use 250 words or less.

(b) Propose how to make the new debug interface secure, the concept of how it would operate and what FPGA resources it would require to be implemented. Use 250 words or less.