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A 6.8MVA, three phase Y-connected synchronous generator has negligible armature resistance and synchronous reactance of 1.2ohm per phase.
The line output voltage is 4.4kV. Calculate the generated e.m.f. And the load angle if the generator operates at its full load under:
a) Lagging power factor of 0.82,
b) Unity power factor,
c) Leading power factor of 0.74
A 5-volt intelligence amplitude causes the frequency to change to ± 25 kHz. What will be the carrier frequency variation corresponding to an intelligence amplitude of 10 volts
Determine the eigenvalues of the system: y1'=8y1-y2 y'2=y1+10y2 What is the stability of the critical point lambda(base)1=2+i2, lambda=2-i2, Stable and attractive
Three single phase transformers with a turns ratio of 1:1 are connected to form a three phase transformer. The transformer input is a three wire three phase 120V (line-to-line) system. the transformer output supplies a "Y" connected three phase lo..
based upon the Norton thevenin equivalentcircuits (Method of short circuit through nodal analysis) When there is a short circuit present, any resistor in parallel will not have current running through it. But what if: 1) A independant current source ..
Two stages are cascaded to result in an overall gain of 680 V/V.The loaded gain of the first stage is 36 dB. What must the gain ofthe second stage be in dB to satisfy this specification In V/V
Heat transfer from the wire to the air is characterized by the convection coefficient h. Obtain an expression for the steady-state temperature distribution T(x) along the wire.
An LED is rated at VF=1.6V to 2.0V at IF=20mA. What value of series resistance is needed to limit the LED current to 20mA when this LED is connected to a 32 v peak source (that is, a source having a peak voltage of 32 v)
Consider a 4 channel CDM system with the following CHIPS: A: -1 -1 -1 1 B: -1 -1 1 -1 C: -1 1 -1 -1 D: -1 1 1 1 a) Show that each one of those chips is orthogonal to all of the others. b) If the CDM signal 1 -1 -3 1 is received, by all receivers, ..
Write the verilog code for a circuit that counts the number of 1s in a byte. Write the verilog code using a structural approach based on four Half-Adders, two 2-bit adders and one 3-bit adder. Write the test bench code to test the design.
A)At what reverse bias voltage does the reverse-bias current in a silicon pn junction diode reach 90 percent of its saturation value B)what is the ratio of the current for a forward-bias voltages of 0.2 V to the current for a reverse- bias voltage o..
(The output generates the 2's complement of the input binary number) Show that the circuit can be constructed using Exclusive-OR gates. Can you predict what the output functions are for a 5-bit 2's complement
define state variables, determine the required initial conditions, and use Matlab to solve for voltages Vc(t) and Vo(t). Plot the results, and verify that the numerical solution using state variables matches the hand calculation solution.
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