Cache-based system experiences

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A cache-based system experiences a cache hit rate of 90%. A cache access requires 1 clock cycle and main-memory access requires 32 clock cycles. Main memory is only accessed after a cache miss. On a cache miss, the cache is updated from main memory and the read is then made from cache. What is the Effective Access Time (EAT) for this system? Give your answer in the form a.b, such as 9.5. Round to the nearest tenth if rounding is necessary.

Reference no: EM133217616

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