Reference no: EM13756782
Processor Performance & Pipeline
Exercise 1
We wish to compare two systems S1 and S2. The table below presents measurements for the two systems when running two programs, Program 1 and Program 2.
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System 1
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System 2
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Program
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ExT (sec)
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IC
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ExT (sec)
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IC
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1
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6
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12x106
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8
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10x106
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2
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10
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6
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1. If the clock rate of system S1 is 4 MHz and the clock rate for system S2 is 6 MHz, find CPI For each system when running Program 1
CPI for S1 = ______________
CPI for S2 = ______________
2. Assuming the CPI for each system when running Program 2 is the same as it is when running Program 1, find the instruction count (IC) for each system when running Program 2
IC for S1 = ______________
IC for S2 = ______________
Exercise 2
Consider a pipelined execution of the following program segment in which the instruction labeled "Beg" starts at memory address (2040)10. All registers used contain 0 initially.
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Beg:
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add
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$8, $9, $10
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beq
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$5, $6, Nex
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lw
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$7, 30($13)
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sw
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$14, 48($15)
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Nex :
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nand
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$11, $12, $13
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1. Show the state of the 5-stage pipeline similar to that of Example 5.16-a) on P. 206 for the instructions above.
2. Assume the time for stages is 100ps for register read or write, and 200ps for other stages. Compute the total time required for each of the instructions used in the program segment above.
3. Compare the total execution time for non-pipelined and pipelined execution of the above program segment:
Non-pipeline design = ______________ ps
Pipelined design = ______________ ps
_________________ design is _________ times faster
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