A non pipeline processor has a clock rate of 25 mhz

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A non pipeline processor has a clock rate of 25 MHz and an average CPI of 4. Processor Y, an improved successor of X, is designed with a 5 stage linear instruction pipeline. However due to latch delay and clock skew effects, the clock rate of Y is only 20MHz, if the program containing 100 instructions is executed on both processors, what is the speed up?

Reference no: EM13752442

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