A current implementation of a particular multicore

Reference no: EM13165382

A current implementation of a particular multicore processor has a 64KB Level one cache for each core, 256KB Level two, and 6MB for level three.

L1 has a cache 8-way associative mapped 32 bytes per line
L2 has a cache 8-way associative mapped 64 bytes per line
L3 has a cache 12-way associative mapped 64 bytes per line

How many bits of main memory byte offset into L1 cache? L2 cache? L3 cache?

How many bits of main memory index into L1 cache? L2 cache? L3 cache?

How many bits of main memory tags into L1 cache? L2 cache? L3 cache?

Reference no: EM13165382

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